Wafer level package and method for manufacturing the same

ABSTRACT

A thermal-stress-absorbing interface structure is provided between a semiconductor integrated circuit chip and a surface-mount structure. The interface structure comprises an elongated conductive-bump pad having a first length-wise end and a second length-wise end, and a side. The pad has an interconnection line extending from the side thereof intermediate the first and the second ends. The interconnection line is electrically connected to the chip. The interface structure further includes a first polymer layer having an exposed surface, and a second polymer layer, each having a different modulus of elasticity, disposed below the pad. The second polymer layer extends over substantially the entire exposed surface of the first polymer layer to absorb a thermal stress during thermal cycling.

[0001] This application is a continuation application of U.S. patentapplication Ser. No. 09/752,856 filed Dec. 29, 2000, which is hereinincorporated by reference in its entirety.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention generally relates to the field ofsemiconductor manufacturing and, more particularly, to a wafer levelpackage (WLP) with improved interconnection reliability and a method formanufacturing the same.

[0004] 2. Description of the Related Art

[0005] In order to meet ever-demanding packaging requirements for newergenerations of electronic products, countless efforts have been expendedto create the most reliable, cost-effective, small, and high-performancepackages. Such requirements are, for example, reductions in propagationdelay and in overall component area as well as broader latitude ininput/output (I/O).

[0006] To meet those requirements, a wafer level package (WLP) has beenrecently developed. In the WLP, unlike the periphery leaded packages, anarray of external terminals is distributed over the semiconductorsurface in place of outer leads of leaded packages. This reduces thesignal path from a semiconductor chip to package I/O location, therebyimproving the electrical performance of the device. Further, the area itoccupies when mounted onto a printed circuit board or other substrate isthe size of the chip. Thus, the size of the WLP is very small.

[0007] For these reasons, almost all WLPs use metallic solder ballsdisposed in an area array fashion to interconnect the package to theprinted circuit board.

[0008] However, due to grossly mismatched coefficient of thermalexpansions (CTE) between the chip and the printed circuit board, if themetallic solder balls, which are minimally elastic, alone were used tointerconnect the chip contacts to the substrate, the strain would beabsorbed by the solder balls, causing them to crack and fail due to themechanical stress of the differential CTE of the chip relative to theprinted circuit board, thereby damaging the reliability of the solderconnection.

[0009] In other words, when the chip heats up during use, both the chipand the board expand, and when the heat is removed, both the chip andthe substrate shrink. The problem that arises is that the chip and thesubstrate expand and contract at different rates and at different times,thereby stressing the interconnections or solder balls between them.

[0010] Some attempts have been made to solve these problems, but theyturned out to be unsuccessful. Moreover, if the chip size becomes large,it has been discovered that the residual stress or displacement at theperiphery of the chip also significantly increases compared to that ofthe center portion of the chip.

[0011] As a result, with conventional structures, experience says thatit is not sufficient to prevent the solder cracking or the breakage ofmetal interconnection at the side of the solder ball pad, especiallynear the edge of the chip.

[0012] Therefore, what is needed is a newly designed WLP with improvedinterconnection reliability, especially between the chip and the board,and a method of manufacturing the same.

SUMMARY OF THE INVENTION

[0013] The present invention provides a thermal-stress-absorbinginterface structure for a WLP and the method of manufacturing the sameto improve interconnection reliability of the WLP such as solder jointreliability.

[0014] According to preferred embodiments of the present invention, athermal-stress-absorbing interface structure between a semiconductorintegrated circuit chip and a surface-mount structure comprises anelongated conductive-bump pad having a first length-wise end and asecond length-wise end, and a side. The thermal-stress-absorbinginterface structure further includes means for allowing the first end ofthe pad to move up when the second end of the pad moves down andalternately allowing the first end to move down when the second endmoves up, upon thermal cycling. The means has a center axis. Theup-and-down movements of the pad are balanced on the center axis. Theinterface structure can include a conductive bump formed on the pad.

[0015] According one aspect of the present invention, a method offorming a WLP is disclosed. The method comprises providing asemiconductor wafer having a plurality of semiconductor chips and aplurality of scribe lines. Each of the semiconductor chips includes aplurality chip pads and a passivation layer thereon. Then, a multi-layerthermal-stress-absorbing support structure is formed over the resultingstructure. Next, a first patterned conductor layer is formed over themulti-layer structure. A first patterned insulation layer is formed overthe first patterned conductor layer. Here, the first patternedinsulation layer includes an opening therein. The opening exposes aportion of the first patterned conductor layer. Then, a conductive bumpis placed over the exposed portion of first patterned conductor layer.Lastly, the wafer is singulated to separate the semiconductor chips tocomplete the WLP.

[0016] Preferably, the multi-layer structure comprises a first polymerlayer and a second polymer layer covering the first polymer layer. Thefirst and second polymer layers and the pad including theinterconnection line, which extends from the side thereof intermediatethe first and the second ends, cooperatively allows the elongatedconductive bump pad to make the up-and-down movements pivoted on thecenter axis and allows the first and second polymers to resilientlydeform corresponding to the up-and-down movements of the pad balanced onthe center axis, upon thermal cycling. This absorbs or dissipatesthermal stresses generated during thermal cycling.

[0017] With these features of the present invention, interconnectionreliability of the WLP can be significantly improved. For example, thethermal stresses generated during the thermal cycling are absorbed ordissipated efficiently without breakage of the joints (physicalconnection) between the conductive bump and the underlying structure.

[0018] The foregoing and other objects, features and advantages of theinvention will become more readily apparent from the following detaileddescription of a preferred embodiment of the invention that proceedswith reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019]FIG. 1 is a cross-sectional view of a thermal-stress-absorbinginterface structure in accordance with one embodiment of the presentinvention.

[0020]FIG. 2 is a plan view of an elongated conductive bump pad and aninterconnection line extending therefrom in accordance with thepreferred embodiment of the present invention.

[0021]FIG. 3 is a cross-sectional view of the thermal-stress-absorbinginterface structure during various stages of thermal cycling, i.e.heating up and cooling down, to show the up-and-down movement of the padto absorb a thermal stress.

[0022]FIG. 4 is a schematic top view of a semiconductor wafer thatincludes semiconductor integrated circuit chips and scribe lines formedthereon.

[0023]FIG. 5 is a cross-sectional view of a part of the semiconductorsubstrate with a passivation layer formed thereon exposing chip pads.

[0024]FIG. 6 is a cross-sectional view showing a patterned polymericlayer formed overlying the passivation layer shown in FIG. 5.

[0025]FIG. 7 is a cross-sectional view showing a patterned metal layerfor electrical interconnection between the chip pads and conductive bumppads including a ground metal layer.

[0026]FIG. 8A is a cross-sectional view showing a first polymer layer toform a thermal-stress-absorbing interface structure in accordance withpreferred embodiment of the present invention.

[0027]FIG. 8B is a plan view corresponding to FIG. 8A.

[0028]FIG. 9 is a cross-sectional view showing a second polymer layerformed overlying the first polymer layer shown in FIG. 7.

[0029]FIG. 10A is a cross-sectional view showing another patterned metallayer for forming a conductive bump pad and an interconnection lineextending therefrom as shown in FIG. 2.

[0030]FIG. 10B is a plan view of FIG. 10A showing a first patternedconductor layer for forming the conductive bump pad and theinterconnection line.

[0031]FIG. 11 is a cross-sectional view showing a patterned dielectriclayer formed overlying the patterned metal layer shown in FIGS. 10A and10B.

[0032]FIG. 12 is a cross-sectional view showing a conductive bump formedoverlying the conductive bump pad.

[0033] It will be appreciated that for simplicity and clarity ofillustration, elements illustrated in the figures have not necessarilybeen drawn to scale. For example, the dimensions of some of the elementsare exaggerated relative to other elements for clarity.

DETAILED DESCRIPTION

[0034] The disclosed preferred embodiment enables formation of a waferlevel package (WLP) having improved interconnection reliability with anovel thermal-stress-absorbing interface structure between asemiconductor chip and a support structure.

[0035] In the following description, numerous specific details are setforth to provide a thorough understanding of the present invention.However, one having ordinary skill in the art should recognize that theinvention could be practiced without these specific details. In someinstances, well-known process steps, device structures, and techniqueshave not been shown in detail to avoid obscuring the present invention.Like numerals are used for like and corresponding parts of the variousdrawings.

[0036] The preferred embodiments of the thermal-stress-absorbinginterface structure 20 of the present invention are best understood byreferring to FIGS. 1-3 of the drawings. It is to be noted that theinvention has been described with the positional relationships betweeneach element shown in FIGS. 1-3 for simplicity. However, one skilled inthe art will appreciate that the invention is not necessarily so limitedand that the positional relationships can be inverted, e.g., thestructure can be up-side-down within the sprit and scope of theinvention.

[0037] Referring to FIGS. 1 and 3, the preferred embodiment of theinvention comprises a thermal-stress-absorbing interface structure 20that is disposed between a semiconductor integrated circuit chip 22 anda surface-mount structure 24. The surface-mount structure 24 can be aconventional printed circuit board or other similar board-type producton which the semiconductor integrated circuit chip 22 can be mounted.

[0038] Preferably, the thermal-stress-absorbing interface structure 20is a generally planar multi-layer structure as shown in FIG. 1. Indetail, the multi-layer structure 20 comprises a first polymer layer 26having an exposed surface and a second polymer layer 28 covering theexposed first polymer layer 26. The first polymer layer 26 is shapedelongated, preferably, a substantially oval shape in plan view asindicated in dotted line 31 of FIG. 2.

[0039] In accordance with one aspect of the present invention, thesecond polymer layer 28 extends at least over substantially the entireexposed surface of the first polymer layer 26 to efficiently help absorbthermal stresses during thermal cycling.

[0040] Preferably, at least two layers of multi-layer structure 20 havedifferent moduli of elasticity. For example, the first polymer layer 26can be formed of a material having a modulus of elasticity ofapproximately 5-200 MegaPascal (MPa) and the second polymer layer can beformed of a material having a modulus of elasticity of approximately1-20 Giga Pascal (GPa). In this respect, the first polymer layer can bean elastomer, or low modulus polymer and the elastomer can be apolysiloxane, or equivalent.

[0041] The first polymer layer is preferably formed to a thickness ofbetween approximately 5-35 μm. Also, according to one embodiment, thesecond polymer layer comprises a polyimide and is formed to a thicknessof approximately 2-50 μm.

[0042] Referring to FIG. 2, the thermal-stress-absorbing interfacestructure 20 includes an elongated conductive-bump pad 30 having a firstlength-wise end 32 and a second lengthwise end 34, and a side 36. Aconductive bump 21 is formed over the elongated bump pad 30 that ispreferably of an oval shape or similar shapes. The elongated bump pad 30further includes an interconnection line 38 extending from the side 36thereof. The interconnection line 38 is disposed intermediate the firstand the second ends 32, 34 along the center axis 25. Here, the ratio ofarea between the first polymer layer and the pad is approximately1.1:1.0. Preferably, the ratio is approximately 1:1 for simplicity offabrication.

[0043] The concept of the present invention is illustrated in FIG. 3.The thermal-stress-absorbing interface structure 20 with featuresdescribed above allows the first end 32 of the elongated bump pad 30 tomove up when the second end 34 of the elongated bump pad 30 moves downand alternately allowing the first end 32 to move down when the secondend 34 moves up, upon thermal cycling (the heating and cooling cycles ofthe chip during operation or reliability test). Thethermal-stress-absorbing structure 20 has a center axis 25 about whichthe up-and-down movements occur. In the present invention, theup-and-down movements of the elongated pad 30 are balanced on the centeraxis 25 to effectively absorb or dissipate the thermal stresses withoutcausing a slip along various physical connections (including thesolder-substrate joint or the solder-pad joint) that could lead tobreakage of the joints during thermal cycling.

[0044] Although the center axis 25 is designated as a certain point inFIG. 3, it is not so limited as such. Any other points that efficientlyallow the up-and-down movements of the elongated bump pad 30 for thepurpose of the present invention can be designated as such, within thespirit and scope of the present invention.

[0045] According to the preferred embodiment of the present invention,it is believed that the interface structure 20 described above includingthe interconnection line 38 disposed intermediate the first and secondends 32, 34 and the first and second polymer layers 26, 28 cooperativelyallows the elongated bump pad 30 to make the up-and-down movementspivoted on the center axis 25 along which the interconnection lineextends. Also, with this interface structure scheme, the first andsecond polymers 26, 28 resiliently deforms accommodating andcorresponding to the up-and-down movements of the elongated bump pad 30,balanced on the center axis 25, upon thermal cycling.

[0046] As a result, thermal stresses generated during the thermalcycling can be significantly absorbed or dissipated as schematicallyillustrated in FIG. 3. Interestingly, it is to be noted that when asingle layer structure is used in place of the multi-layer structure 20,the up-and-down movements on the center axis 25 that occur with themulti-layer structure 20 do not occur sufficiently, thus resulting insolder joint failures. It is believed that the multi-layer structure 20of the preferred embodiment help such up-and-down movements to occur,thereby reducing thermo-mechanical stresses applied to the joints.Especially, when the modulus of elasticity of the material for the firstpolymer layer is 20 times smaller than that of the material for thesecond polymer layer, the multi-layer structure 20 shows better stressabsorption characteristics compared to other cases.

[0047] Such effects and advantages of the present invention can befurther explained as follows. It is known that the number of shearstress-strain cycles a solder joint can experience before failing iscorrelated with the damage to the solder-substrate joint. See“Energy-Based Methodology for the Fatigue Life Prediction of SolderMaterials,” IEEE Transactions On Components, Hybrids, and ManufacturingTechnology, Vol. 16, No. 3, pp. 317, 1993. The damage function isdefined as the product of the shear stress and the shear strain, i.e.,the work performed on the solder in the plastic deformation cycle. Withrepeated cycling, the damage accumulates and the joint fails. Reducingshear strain reduces solder damage, and extends solder joint life.Reducing the shear stress reduces the shear strain.

[0048] In view of this, it is believed that, together with theup-and-down movements of the elongated bump pad 30 and the resilientdeformation of the first and second polymers 26, 28 accommodating theup-and-down movements of the pad, balanced on the center axis 25, uponthermal cycling, the conductive bump 21 maintains a normal, i.e.substantially perpendicular, relationship with respect to a plane of thesurface-mount structure 24 without the slip or breakage along thevarious joints including the solder-substrate joint or the solder-padjoint.

[0049] Thus, with the preferred embodiments of present invention, thestresses applied to the various joints can be significantly dissipatedor reduced. Accordingly, interconnection reliability can besignificantly improved in accordance with the present invention.

[0050] In this respect, a person skilled in the art will appreciate thatother means to allow the up-and-down movements of the elongated bump pad30 pivoted on the center axis thereof and to allow the conductive bump21 to maintain a normal, i.e. substantially perpendicular, relationshipwith respect to a plane of the surface-mount structure 24 withoutbreakage of the joints can be used in place of the generally planarmulti-layer structure 20 for the purpose of the present invention.

[0051] Further, according to the present invention, the wave action onthe pad 30 resulting from the up-and-down movements of the pad 30produces only torsion-substantially no compression or tension-on theinterconnection line 38 due to the position and orientation of theinterconnection line 38 relative to the center axis 25. In other words,because the up-and-down movements of the elongated bump pad 30 is basedon the center axis 25 pivoted along the direction of the interconnectionline 38, the breakage of the interconnection line 38 can besubstantially reduced. Because the connection line 38 extends from thecenter of elongated pad 30, the intermediate portion or center of theelongated bump pad 30 has very low displacement during waving of theelongated bump pad 30 due to thermal cycling.

[0052] The present invention semiconductor interface structure can alsobe characterized as an interface structure comprises an elongatedconductive-bump pad 30 having a long axis 33 and a short axis 35, asupport structure 26 having, in cross-section, a dome-shape or a dome5shaped edge with a substantially flat top surface. See FIGS. 2 and 8A.Here, the support structure 26 underlying the pad 30 is configured torock about the short axis 35 during thermal cycling to mitigate thestress of CTE mismatch.

[0053] The interface structure can also include a polymer layer 28covering the dome-shaped support structure 26. Preferably, thedome-shaped support structure 26 comprises an elastomer and the polymerlayer 28 comprises a polyimide. See FIG. 8A. Similar to the embodimentsdescribed above, the pad 30 is an oval shape in plan view and the pad 30has an interconnection line 38 extending from the center thereof alongthe short axis 35.

[0054] FIGS. 4-12 illustrates a method for manufacturing a wafer levelpackage (WLP) incorporating a thermal-stress-absorbing interfacestructure in accordance with preferred embodiment of the presentinvention. Details of the manufacturing steps are omitted if they areconventional or well known for clarity and simplicity.

[0055] As shown in FIG. 4, in order to fabricate a WLP, a semiconductorwafer 40 having a plurality of semiconductor integrated circuit chips 22and scribe lines 44 between the semiconductor chips 22 is provided.

[0056] Turning to FIG. 5, on the semiconductor wafer 40, a patternedpassivation layer 52 exposing a plurality of semiconductor chip pads 54is formed using conventional techniques. The patterned passivation layercan be formed of a conventional material such as silicon nitride.

[0057] After these steps, as shown in FIG. 6, in accordance with oneembodiment, a second patterned insulation layer 62 is formed over thepassivation layer 52 using conventional techniques such as soft cure,exposure, development and hard cure. The second patterned insulationlayer 62 is formed of a polymer such as a polyimide. Preferably, thesecond patterned insulation layer 62 has a thickness of approximately2-50 μm.

[0058] Now referring to FIG. 7, a second patterned conductor layer 72 isformed over the second patterned insulation layer 47 as a reroutingmetallization. The rerouting metallization typically comprises aluminumor copper and is formed to reroute the chip pads 54 in an area arrayconfiguration. The thickness of the second patterned conductor layer 72is preferably approximately 1-20 μm. Preferably, the second patternedconductor layer 72 comprises a mesh-patterned metal layer 71,illustrated in FIG. 8B, such that the adhesion, impedance andcapacitance between the second patterned conductor layer 72 and a secondpolymer layer 28 (to be formed thereon) can be improved. The secondpatterned conductor layer 72 is preferably formed by a core layer ofcopper covered with a material such as Cr, Ti, TiN, TaN or WN.Alternatively, the second patterned conductor layer can be formed of amaterial such as aluminum, nickel, silver, copper, copper alloys,aluminum alloys and nickel alloys.

[0059] Next, as shown in FIGS. 8A-9, multi-layer structures 27comprising first and second polymer layers 26, 28 for fabricatingthermal-stress-absorbing interface structure 20, shown in FIG. 1, areformed over the resulting structure in accordance with preferredembodiment of the present invention. The multi-layer structures 27provide more protection to the semiconductor chips 22 from externalshock and thermo-mechanical damage applied to joints or interconnectionlines of the WLP during reliability test and actual use. Preferably, themulti-layer structures 27 are fabricated by forming the first polymerlayer 26 over the second patterned conductor layer 72, and by coveringthe first polymer layer 26 with a second polymer layer 28. The firstpolymer layer 26 is formed by conventional techniques such as spincoating and subsequent etching, or by screen-printing.

[0060] After these process steps, as shown in FIG. 8B, the first polymerlayer 26 having a substantially oval shape in plan view and a dome orsimilar shape in cross section can be produced.

[0061] Then, as shown in FIGS. 10A and 10B, a first patterned conductorlayer 102 is formed over the multi-layer structure 27 comprising thefirst and second polymer layers 26, 28 for forming signal lines 29 and aconductive bump pad 30.

[0062] According to one aspect of the present invention, in this step,an elongated conductive bump pad 30 is formed having a first length-wiseend 32 and a second length-wise end 34. Here, the pad 30 includes aninterconnection 38 extending from the side 36 thereof intermediate thefirst and the second ends 32, 34. See FIG. 2.

[0063] The first patterned conductor layer 102 preferably comprisesCr/Cu/Cu/Ni. Alternatively, the first patterned conductor layer can beformed of a material such as aluminum, nickel, copper, silver, copperalloys, aluminum alloys and nickel alloys. In addition, the firstpatterned conductor layer is preferably formed to a thickness of 1-20μm. The first patterned conductor layer 102 can be formed in combinationwith etching and one of sputtering, evaporating or electroless plating.

[0064] Also, as shown FIG. 10B, the plurality of elongated conductivebump pads 30 is disposed in a substantially radial fashion to betteraccommodate the flexure due to CTE mismatch. Here, an underbumpmetallurgy (not shown) can be formed over each of the elongated bumppads 30.

[0065] Turning to FIG. 11, a first patterned insulation layer 112 isformed over the first patterned conductor layer 102. Further, the firstpatterned insulation layer 112 has an opening 114 therein. The opening114 exposes a portion of the first patterned conductor layer 112 whereconductive bumps 21 is to be mounted.

[0066] Referring to FIG. 12, the conductive bumps 21 are subsequentlyformed over the exposed portion of first patterned conductor layer 102.The conductive bump 21 can be a conventional solder ball. Alternatively,other metal bumps such as gold wire stud bumps and electrolessnickel/gold plated bumps, or conductive polymer bumps can be used.

[0067] Finally, the wafer is singulated to separate the semiconductorchips to complete a WLP in accordance with scribe lines 44 shown in FIG.4.

[0068] In the present invention, the first polymer layers 26 ofmulti-layer structures 27 are physically separated from each other sothat each individual multi-layer structure 27 can be deformed toaccommodate the movements of the associated pad without interferencefrom one another as shown in FIG. 8B.

[0069] Although FIGS. 4-12 have been described including the formationof the second patterned conductor layer 72 for rerouting metallization,the present invention can be implemented without the formation of thesecond patterned conductor layer 72, if necessary or desirable.

[0070] The WLP incorporating a thermal-stress-absorbing interfacestructure made in accordance with the present invention significantlyenhances interconnection reliability as noted above. Also, it isbelieved that the interface structure of the present invention absorbsor dissipates various stresses including thermal stress applied to thevarious joints when the WLP is mounted on a printed circuit board andused for an extended period. This will extend the life of the WLP, andvarious electronic products such as cellular phones incorporating WLP.

[0071] Having described and illustrated the principles of the inventionin a preferred embodiment thereof, it should be apparent that theinvention can be modified in arrangement and detail without departingfrom such principles. I claim all modifications and variation comingwithin the spirit and scope of the following claims.

What is claimed is:
 1. A thermal-stress-absorbing interface structurebetween a semiconductor integrated circuit chip and a surface-mountstructure, the structure comprising: an elongated conductive-bump padhaving a first length-wise end and a second length-wise end, and a side,the pad having an interconnection line extending from the side thereofintermediate the first and the second ends, the interconnection linebeing electrically connected to the chip; and a first polymer layerhaving an exposed surface, and a second polymer layer, each having adifferent modulus of elasticity, disposed below the pad, the secondpolymer layer extending over substantially the entire exposed surface ofthe first polymer layer to absorb a thermal stress during thermalcycling.
 2. The structure of claim 1, further comprising a conductivebump over the pad, wherein the conductive bump is mounted on thesurface-mount structure.
 3. The structure of claim 2, wherein theconductive bump maintains a normal relationship with respect to a planeof the surface-mount structure upon thermal cycling.
 4. The structure ofclaim 1, wherein the first polymer layer comprises an elastomer.
 5. Thestructure of claim 4, wherein the elastomer comprises a polysiloxane. 6.The structure of claim 1, wherein the first polymer is formed to athickness of between approximately 5-35 μm.
 7. The structure of claim 1,wherein the second polymer layer comprises a polyimide.
 8. The structureof claim 7, wherein the polyimide second polymer layer is formed to athickness of approximately 2-50 μm.
 9. The structure of claim 1, whereinthe first polymer layer is a substantially oval shape in plan view. 10.The structure of claim 1, wherein the conductive bump pad has an ovalshape in plan view.
 11. A semiconductor interface structure, comprising:an elongated conductive-bump pad having a long axis and a short axis; asupport structure having, in cross-section, a dome-shape, the supportstructure underlying the pad configured to rock about the short axisduring thermal cycling.
 12. The semiconductor interface structure ofclaim 11, further comprising: a polymer layer covering the dome-shapedsupport structure.
 13. The semiconductor interface structure of claim12, wherein the dome-shaped support structure comprises an elastomer andthe polymer layer comprises a polyimide.
 14. The semiconductor interfacestructure of claim 11, wherein the pad is an oval shape in plan view.15. The semiconductor interface structure of claim 11, wherein the padhas an interconnection line extending from the center thereof along theshort axis.
 16. A semiconductor assembly, comprising: a semiconductorintegrated circuit chip having a plurality of chip pads and apassivation layer; a plurality of elongated conductive bump pads, eachof the pads having a first lengthwise end and a second length-wise end,each pad having an interconnection line extending from the side thereofintermediate the first and the second ends, the interconnection linebeing electrically connected to the chip; and a plurality of multi-layerthermal-stress-absorbing structures each disposed below one of the pads,each of the multi-layer structures having a center axis, wherein each ofthe multi-layer structures comprises: a first polymer layer, and asecond polymer layer covering the first polymer layer.
 17. Thesemiconductor assembly of claim 16, wherein the first and second polymerlayers and the pad including the interconnection line extending from theside thereof intermediate the first and the second ends along the centeraxis cooperatively allows the first end of the pad to move up when thesecond end of the pad moves down and alternately allows the first end tomove down when the second end moves up upon thermal cycling, the firstand second polymers resiliently deformable accommodating the up-and-downmovements of the pad, upon the thermal cycling, to absorb thermal stressgenerated during thermal cycling, whereby the up-and-down movements ofthe pad and the deformation of the first and second polymers arebalanced on the center axis.